Synthesis result and debugging

Common errors due to synthesis:

Download the project files

All UCI faculty and students can download from this location

Use the following links to access the corresponding files:

/jmoorkan/begenet/begenet.rar:
https://webfiles.uci.edu/xythoswfs/webui/_xy-3281212_1

/jmoorkan/begenet/EECS 275 VLSI project report.doc:
https://webfiles.uci.edu/xythoswfs/webui/_xy-3281213_1

/jmoorkan/begenet/EECS 275A Project Report.pdf:
https://webfiles.uci.edu/xythoswfs/webui/_xy-3281215_1

Others kindly email or add a comment to this blog and I will contact back.

Memory cell design

http://www.rulabinsky.com/cavd/text/chap11-6.html
http://www.cedcc.psu.edu/khanjan/vlsispec.htm
http://www-unix.ecs.umass.edu/~rramanar/Lab4.htm
http://larc.ee.nthu.edu.tw/~dtc/doc/940603.pdf
https://intranet.insa-toulouse.fr/view/422/content/memory_world.html

Things to do

(1) Convert information in GDS format to Magic layout format
(2) Dump the results of the Random Number logic in Verilog and import it to C++/C implementation. And check whether the C/c++ code matches correctly with the Verilog implementation. The format of the output should be the following
seed=1010101
tapConfig=0101010
100101
101010
101010
010010

Either the outputs will be dumped to different text file, or will be put into a single file.
(3) Find a tool flow for memory compilation ?

Pseudo Random HW design choices A

Standard names Correct naming:

1. dataIn
2. clock
3. dataOut
4. rst = Reset
5. feedbkEna = Feed Back Enable
6. tapConfigIn
7. tapConfigEna
8. RandType

Design issues:

(1) Parallel input configuration vs serial input configuration

(2) Mulitplexed input pins vs dedicated input pins

(3) Parallel output data vs serial output data

(4) Basic functionality which is required:

(a) Programmable SEED value register. This will decide the initial value which need to be loaded in the LFSR. Another pin will be used called "program_seed" to indicate availabilty of new seed value.

(b) Shift Enable pin to freeze the random number generator to a particular value. When Shift Enable is '1', then a new random number is generated in the next clock cycle.

(d)


(1) Use a simple FIXED 2 TAP generator

(2) Use a simple FIXED 5 TAP generator

Pseudo Random notes

Random-number-generator-algorithms
Robert M. Ziff, “Four-tap shift-register-sequence random-number generators”,
Xilinx Notes on LFSR http://www.xilinx.com/bvdocs/appnotes/xapp052.pdf
http://www.intuitor.com/statistics/Simulations.html
Tutorials on LFSR
http://en.wikipedia.org/wiki/LFSR
New Xilinx LFSR Manual

http://www.cs.wm.edu/~va/software/park/park.html
http://academic.csuohio.edu:8080/chup/chu_web_stuff/research_stuff/Random.PDF
Article on implementation: http://www.techonline.com/community/ed_resource/feature_article/38012
http://www.wolframscience.com/nksonline/page-974b-text?firstview=1
Random library appendix

Tap Coefficients Table

Demo of RTL to GDS2 in EECS 275A

Demonstration of going from behavioral verilog upto complete GDS using AMI0.5u library
for EECS 275A project course:

Project type: algo_lfsr

1. ./compile.sh

newport% more compile.sh
ncvlog -work work -linedebug rtl/def_param.v rtl/algo_auto_lfsr_core.v
ncvlog -work work -linedebug rtl/toplevel.v
ncelab work.toplevel -access +rw
#ncsim -gui work.toplevel

2. more sim.h

ncsim work.toplevel -tcl -input tcl/ncsim.tcl

3. ./sim.h
ncsim: 05.50-s002: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
ncsim> database -open mywave -shm -default
Created default SHM database mywave
ncsim> probe -create -shm -all -variables -depth all
Created probe 1
ncsim> run
9
203
170
85
229
189
145
135
140
70
35
222
111
248
124
62
31
192
96
48
24
12
6
3
206
103
252
126
63
208
Simulation complete via $finish(1) at time 3100 NS + 0
./rtl/toplevel.v:33 #end_time $finish;
ncsim> database -close mywave
ncsim> finish

3. more tcl/ncsim.tcl
database -open mywave -shm -default
probe -create -shm -all -variables -depth all
run
database -close mywave
finish

4. Use the command simvision to look into the output wave and open the file "mywave".

>> simvision

4. more tcl/algo_auto_lfsr_pks.tcl

# All VHDL files, separated by spaces
#set my_vhdl_files {./rtl/regfile.vhd}
set my_verilog_files {./rtl/def_param.v ./rtl/algo_auto_lfsr_core.v}

# Top-level Module
set my_toplevel_module algo_auto_lfsr_core

# The name of the clock pin. If no clock-pin
# exists, pick anything
set my_clock_pin clk

# Target frequency in MHz for optimization
set my_clock_freq_MHz 100

# Delay of input signals (Clock-to-Q, Package etc.)
set my_input_delay_ns 1

# Reserved time for output signals (Holdtime etc.)
set my_output_delay_ns 1

....


5. pks_shell -f tcl/algo_auto_lfsr_pks.tcl

Restarting optimization loop. .
+--------------------------------------------------------------+
| Path Group Options Report |
|--------------------------------------------------------------|
| PathGroup | Effort | All | Target | Critical | Worst | TEFS |
| | | Pts | Slack | Endpoints | Slack | |
|-----------+--------+-----+--------+-----------+-------+------|
| default | medium | - | 0.00 | 0/24 | 8.09 | 0.00 |
+--------------------------------------------------------------+
+--------------------------------------------------------------+
| Path Group Options Report |
|--------------------------------------------------------------|
| PathGroup | Effort | All | Target | Critical | Worst | TEFS |
| | | Pts | Slack | Endpoints | Slack | |
|-----------+--------+-----+--------+-----------+-------+------|
| default | medium | - | 0.00 | 0/24 | 8.09 | 0.00 |
+--------------------------------------------------------------+
Command do_optimize finished at Sun Apr 16 04:27:53 2006
using 0:0:2 Real time. Current peak memory: 26.562MB .
--> WARNING: Writing VHDL netlist for module 'algo_auto_lfsr_core' with std_
logic and std_logic_vector ports" .

newport% more compile_post.sh
echo '`'timescale 1ns/10ps > output/tmp.v
cat output/algo_auto_lfsr_core.v >> output/tmp.v
mv output/tmp.v output/algo_auto_lfsr_core.v
ncvlog -work work -linedebug rtl/def_param.v output/algo_auto_lfsr_core.v
ncvlog -work work -linedebug rtl/toplevel.v
ncvlog -work work -linedebug rtl/def_param.v /ecelib/eceware/cadence04/othertools/stdcells/ami035/lib/iit035_stdcells.v
ncelab work.toplevel -access +rw
#ncsim -gui work.toplevel

newport% ./compile_post.sh
ncvlog: 05.50-s002: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
ncvlog: 05.50-s002: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
ncvlog: 05.50-s002: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
ncelab: 05.50-s002: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
$recovery(posedge R, posedge CLK &&& \D&S , trec$R$CLK, NOTIFIER);
|
ncelab: *W,CUNGL1 (/ecelib/eceware/cadence04/othertools/stdcells/ami035/lib/iit035_stdcells.v,361|58): Negative timing check limit not allowed in a 1 limit timing check, setting to 0 in instance (toplevel.mod.y_reg_8).
$recovery(posedge R, posedge CLK &&& \D&S , trec$R$CLK, NOTIFIER);

newport% ./sim.sh
ncsim: 05.50-s002: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
ncsim> database -open mywave -shm -default
Created default SHM database mywave
ncsim> probe -create -shm -all -variables -depth all
Created probe 1
ncsim> run
9
203
170
85

newport% cd tcl

newport% encounter -init tcl/encounter.tcl

Verification Complete : 0 Viols. 0 Wrngs.

**********End: VERIFY GEOMETRY**********
*** verify geometry (CPU: 0:00:00.2 MEM: 0.0M)


******** Start: VERIFY CONNECTIVITY ********
Start Time: Sun Apr 16 04:40:53 2006

Design Name: algo_auto_lfsr
Database Units: 1000
Design Boundary: (0.0000, 0.0000) (193.6000, 184.0000)
Error Limit = 1000; Warning Limit = 50
Check all nets

Begin Summary
Found no problems or warnings.
End Summary

End Time: Sun Apr 16 04:40:53 2006
******** End: VERIFY CONNECTIVITY ********
Verification Complete : 0 Viols. 0 Wrngs.
(CPU Time: 0:00:00.0 MEM: 0.000M)

**************************************
* Encounter script finished *
* *
* Results: *
* -------- *
* Layout: final.gds2 *
* Netlist: final.v *
* Timing: timing.rep.5.final ** *
* Type 'win' to get the Main Window *
* or type 'exit' to quit *
* *
**************************************

newport% more compile_with_io.sh
echo ncvlog -work work -linedebug rtl/def_param.v output/algo_auto_lfsr_core.v rtl/algo_auto_lfsr.v rtl/toplevel.v
ncvlog -work work -linedebug rtl/def_param.v output/algo_auto_lfsr_core.v rtl/algo_auto_lfsr.v rtl/toplevel.v
echo ncvlog -work work -linedebug rtl/def_param.v output/algo_auto_lfsr_core.v rtl/algo_auto_lfsr.v
ncvlog -work work -linedebug rtl/def_param.v output/algo_auto_lfsr_core.v rtl/algo_auto_lfsr.v
echo ncvlog -work work -linedebug rtl/def_param.v /ecelib/eceware/cadence04/othertools/stdcells/ami035/lib/iit035_stdcells.v
ncelab work.toplevel -access +rw
#ncsim -gui work.toplevel

newport% ./compile_with_io.sh
ncvlog -work work -linedebug rtl/def_param.v output/algo_auto_lfsr_core.v rtl/algo_auto_lfsr.v rtl/toplevel.v
ncvlog: 05.50-s002: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
ncvlog -work work -linedebug rtl/def_param.v output/algo_auto_lfsr_core.v rtl/algo_auto_lfsr.v
ncvlog: 05.50-s002: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
ncvlog -work work -linedebug rtl/def_param.v /ecelib/eceware/cadence04/othertools/stdcells/ami035/lib/iit035_stdcells.v
ncelab: 05.50-s002: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
$recovery(posedge R, posedge CLK &&& \D&S , trec$R$CLK, NOTIFIER);
|

newport% ./sim.sh
ncsim: 05.50-s002: (c) Copyright 1995-2005 Cadence Design Systems, Inc.
ncsim> database -open mywave -shm -default
Created default SHM database mywave
ncsim> probe -create -shm -all -variables -depth all
Created probe 1
ncsim> run
9
203
208
Simulation complete via $finish(1) at time 3100 NS + 0
./rtl/toplevel.v:33 #end_time $finish;
ncsim> database -close mywave
ncsim> finish

newport% simvision &
[1] 22181

" check presence of new modules "

newport% encounter -init tcl/encounter.tcl

newport% encounter -init encounter.tcl
This version requires license using cdslmd daemon.
Checking out Encounter license ...
SOC_Encounter_GPS license checkout succeeded.
INFO: Enable Encounter GPS.
Starting console server on port newport.eecs.uci.edu:8888 ..
sourcing /ecelib/eceware/cadence04/soc41/tools/fe/etc/rdaDSL.tcl
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